1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device and a semiconductor system having the same.
2. Description of the Related Art
A semiconductor device (hereinafter, referred to as a “memory device”) such as a Dynamic Random Access Memory (DRAM) performs a series of operations for storing or reading data according to control of a controller.
FIG. 1A is a timing diagram for explaining an operation of a memory device to store data.
Referring to FIG. 1A, when commands CMD for a first active operation ACT0, a first write operation WT0, and a first precharge operation PRE0 are sequentially applied from a controller, the memory device sequentially generates an active command ACT for the first active operation ACT0, a write command CASP for the first write operation WT0, and a precharge command PRE_CMD for the first precharge operation PRE0 at predetermined times in response to the respective commands CMD. Similarly, when commands CMD for a second active operation ACT1, a second write operation WT1, and a second precharge operation PRE1 are sequentially applied, the memory device sequentially generates an active command ACT for the second active operation ACT1, a write command CASP for the second write operation WT1, and a precharge command PRE_CMD for the second precharge operation PRE0 at predetermined times, in response to the respective commands CMD.
At this time, the memory device activates a row of a predetermined bank, for example, a word line, in response to the active command ACT, performs a write operation through a predetermined column, for example, a bit line, in response to the write command CASP, and performs an operation of precharging the predetermined bank in response to the precharge command PRE_CMD.
FIG. 1B is a timing diagram for explaining an operation of the memory device to read data.
Referring to FIG. 1B, when commands CMD for a first active operation ACT0, a first read operation RD0, and a first precharge operation PRE0 are sequentially applied from the controller, the memory device sequentially generates an active command ACT for the first active operation ACT0, a read command CASP for the first read operation RD0, and a precharge command PRE_CMD for the first precharge operation PRE0 at predetermined times, in response to the respective commands CMD. Similarly, when commands CMD for a second active operation ACT1, a second read operation RD1, and a second precharge operation PRE1 are sequentially applied from the controller, the memory device sequentially generates an active command ACT for the second active operation ACT1, a read command CASP for the second read operation RD1, and a precharge command PRE_CMD for the precharge operation PRE0 at predetermined times, in response to the respective commands CMD.
At this time, the memory device activates a row of a predetermined bank, for example, a word line, in response to the active command ACT, performs a read operation through a predetermined column, for example a bit line, in response to the read command CASP, and performs an operation of precharging the predetermined bank in response to the precharge command PRE_CMD.
The memory device operating as described above performs one operation, for example, active operation, read operation, or precharge operation, per one command CMD applied from the controller,